Photo Credits: AMD
- “Excavator” CPU core
- 8 AMD Radeon cores
- 5% more instructions per clock
AMD claims that Carrizo will offer double-digit improvements in performance and battery life compared to Kaveri
One of the major announcements of AMD last month was regarding Carrizo, the new chip for notebooks and low-power desktops, which the company claims is majorly going to cut power consumption as compared to the Kaveri chips. This Monday the chip maker further elaborated on how exactly this is going to be made possible. Unfortunately, we will still have to wait a bit longer till we can learn the exact power consumption or the performance of the Carrizo chip however some hints have been dropped in on us already.
The manufacturer isn’t just talking about some minor enhancements to the power game but this is actually about Carrizo showing double-digit improvements in performance as well as battery life as opposed to Kaveri which was designed as a direct competitor of Intel’s midrange Core i5 chips in January 2014.
Though battery life and its enhancement has been the prime goal of AMD while designing their new chip, but the performance hasn’t been sidelines due to this and it remains equally important. All eyes are set for the International Solid-State Circuits Conference in San Francisco where AMD is going to release its Carrizo paper.
Prior to this big event, Sam Naffziger, an AMD fellow, revealed in an interview “Although we’re just as concerned with performance as we have been, it’s mainly about performance per watt. But most of the form factors that are in the market today are power constrained.”
So far we know that the Carrizo APU is going to be made up of “Excavator” CPU cores and the number of this hasn’t been disclosed as yet. Apart from this, it will have eight AMD Radeon cores which are going to work as an integrated graphics chip. During the Monday announcement, AMD also mentioned that these Excavator cores will execute 5 percent more instructions per clock as compared to Kaveri and as a result of this it will consume 40 percent less power across 23 percent less die area which is 3.1 billion transistors in all.
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